1. Field of the Invention
General, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of field effect transistors having a channel region with a specified intrinsic stress so as to improve the charge carrier mobility.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements such as, e.g., transistors, capacitors and resistors. These elements are connected internally to form complex circuits, such as memory devices, logic devices and microprocessors. The performance of integrated circuits may be improved by increasing the number of functional elements in the circuit in order to increase their functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence allowing an extension of the functionality of the circuit, and also reduces signal propagation delays, thus making an increase of the speed of operation of circuit elements possible. In modern semiconductor structures, features having a critical dimension of 90 nm or less, or even 65 nm or less, may be formed.
Field effect transistors are used as switching elements in integrated circuits. They allow control of a current flowing through a channel region located between a source region and a drain region. The source region and the drain region are highly doped. In N-type transistors, the source and drain regions are doped with an N-type dopant. Conversely, in P-type transistors, the source and drain regions are doped with a P-type dopant. The doping of the channel region is inverse to the doping of the source region and the drain region. The conductivity of the channel region is controlled by a gate voltage applied to a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. Depending on the gate voltage, the channel region may be switched between a conductive “on” state and a substantially non-conductive “off” state.
When reducing the size of field effect transistors, it is important to maintain a high conductivity of the channel region in the “on” state. The conductivity of the channel region in the “on” state depends on the dopant concentration in the channel region, the mobility of the charge carriers, the extension of the channel region in the width direction of the transistor and on the distance between the source region and the drain region, which is commonly denoted as “channel length.” While a reduction of the width of the channel region leads to a decrease of the channel conductivity, a reduction of the channel length enhances the channel conductivity. An increase of the charge carrier mobility leads to an increase of the channel conductivity.
As feature sizes are reduced, the extension of the channel region in the width direction is also reduced. A reduction of the channel length entails a plurality of issues associated therewith. First, advanced techniques of photolithography and etching have to be provided in order to reliably and reproducibly create transistors having short channel lengths. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the source region and in the drain region in order to provide a low sheet resistivity and a low contact resistivity in combination with a desired channel controllability.
In view of the problems associated with a further reduction of the channel length, it has been proposed to also enhance the performance of field effect transistors by increasing the charge carrier mobility in the channel region. In principle, at least two approaches may be used to increase the charge carrier mobility.
First, the dopant concentration in the channel region may be reduced. Thus, the probability of scattering events of charge carriers in the channel region is reduced, which leads to an increase of the conductivity of the channel region. Reducing the dopant concentration in the channel region, however, significantly affects the threshold voltage of the transistor device. This makes the reduction of dopant concentration a less attractive approach.
Second, the lattice structure in the channel region may be modified by creating tensile or compressive stress. This leads to a modified mobility of electrons and holes, respectively. A compressive stress in the channel region increases the mobility of holes. Depending on the magnitude of the compressive stress, an increase of the hole mobility of up to 15% may be achieved. In a P-type transistor, this leads to a corresponding increase of the conductivity of the channel region. Conversely, a tensile stress in the channel region increases the mobility of electrons. Thus, the performance of N-type transistors may be enhanced by providing a tensile stress in the channel region.
A method of forming a semiconductor structure comprising field effect transistors having stressed channel regions according to the state of the art will be described with reference to FIGS. 1a-1b. FIG. 1a shows a schematic cross-sectional view of a semiconductor structure 100 in a first stage of the prior art manufacturing process.
The semiconductor structure 100 comprises a substrate 101, a first transistor element 102 and a second transistor element 202. A trench isolation structure 103 provides electrical insulation between the first transistor element 102 and the second transistor element 202.
The first transistor element 102 comprises a gate electrode 106 and an active region 104. A gate insulation layer 105 separates the gate electrode 106 from the active region 104 and electrically insulates the gate electrode 106 from the active region 104. Adjacent the gate electrode 106, a sidewall spacer structure 112, a source region 107 and a drain region 108 are formed. In the source region 107, in the drain region 108 and at the top surface of the gate electrode 106, silicide regions 109, 110, 111 may be formed.
Similar to the first transistor element 102, the second transistor element 202 may comprise an active region 204, a gate electrode 206, a gate insulation layer 205, a source region 207, a drain region 208, a sidewall spacer structure 212 and silicide regions 209, 210, 211.
The first transistor element 102 and the second transistor element 202 may be transistors of a different type. For example, the first transistor element 102 may be a P-type transistor and the second transistor element 202 may be an N-type transistor.
As persons skilled in the art know, the above-described features may be formed by means of well-known techniques of photolithography, etching, ion implantation, deposition, oxidation and annealing.
An etch stop layer 113 is formed over the semiconductor structure 100. The etch stop layer 113 may comprise a dielectric material such as, for example, silicon nitride, and may be formed by means of known deposition techniques, such as plasma enhanced chemical vapor deposition (PECVD). The etch stop layer 113 may comprise an intrinsic stress.
In plasma enhanced chemical vapor deposition, the semiconductor structure 100 is provided in a reactor vessel, and a reactant gas is supplied to the reactor vessel. In the reactant gas, a glow discharge is created by applying a radio frequency alternating voltage between electrodes provided in the reactant gas or by inductively coupling the radio frequency alternating voltage to the reactant gas. In addition to the radio frequency alternating voltage, a bias voltage, which may be a direct voltage or a low frequency alternating voltage, may be applied. In the glow discharge, chemically reactive species such as atoms, molecules and ions may be created from the reaction gas. The reactive species may react with each other on the surface of the semiconductor structure 100 or in the vicinity thereof. In the reaction, the material of the etch stop layer may be formed and may be deposited on the semiconductor structure 100.
Properties of the etch stop layer 113 may be controlled by varying parameters of the plasma enhanced chemical vapor deposition process, such as power and frequency of the radio frequency alternating voltage and the bias voltage, temperature and pressure in the reactor vessel, and the composition of the reactant gas. In particular, the intrinsic stress of the etch stop layer 113 may be controlled by varying these parameters. Parameter sets which allow obtaining a predetermined tensile or compressive stress in the etch stop layer 113 are known.
The intrinsic stress of the etch stop layer 113 may act on the transistor elements 102, 202 below the etch stop layer 113. Thus, a stress may be created in the substrate 101, in particular in portions of the substrate 101 below the gate electrodes 106, 206 wherein channel regions of the transistor elements 102, 202 will be formed. Hence, stressed channel regions may be provided in the first transistor element 102 and the second transistor element 202.
After the formation of the etch stop layer 113, a layer 114 of a dielectric material may be formed over the semiconductor structure 100 by means of known deposition techniques, such as chemical vapor deposition or plasma enhanced chemical vapor deposition. The dielectric material in the layer 104 may be selected such that the material of the etch stop layer 113 and the material of the layer 114 may be selectively etched. In examples of methods of forming a semiconductor structure according to the state of the art wherein the etch stop layer 113 comprises silicon nitride, the layer 114 comprises silicon dioxide and does not comprise an intrinsic stress.
FIG. 1b shows a schematic cross-sectional view of the semiconductor structure 100 in a later stage of the manufacturing process. After the formation of the layer 114, a chemical mechanical polishing process may be performed to planarize the layer 114. As persons skilled in the art know, in chemical mechanical polishing, the semiconductor structure 100 is moved relative to a polishing pad. A slurry comprising a chemical compound adapted to react chemically with the material of the layer 114 is supplied to an interface between the semiconductor structure 100 and the polishing pad. Products of the chemical reaction may be removed by abrasives contained in the slurry and/or in the polishing pad. In the chemical mechanical polishing process, a surface of the layer 114 is rendered substantially planar.
After the chemical mechanical polishing process, contact vias 115, 116, 117 are formed and filled with an electrically conductive material such as tungsten to provide electrical connections to the source region 107, the gate electrode 106 and the drain region 108 of the first transistor element 102. Similarly, contact vias 118, 119, 120 may be formed to provide electrical connections to the source region 207, the gate electrode 206 and the drain region 208 of the second transistor element 202.
To this end, a mask (not shown) may be formed over the semiconductor structure 100. The mask has openings at the locations at which the contact vias 115-120 are to be formed. Thereafter, an etch process adapted to selectively remove the material of the layer 114, leaving the material of the etch stop layer 113 substantially intact, may be performed. Due to the selectivity of the etch process, the etch process stops as soon as the etch front reaches the etch stop layer 113.
Thereafter, portions of the etch stop layer at the bottom of the contact vias 115-120 may be removed by means of an etch process adapted to selectively remove the material of the etch stop layer 113, leaving the materials of the layer 114 and the silicide regions 109, 110, 111, 209, 210, 211 substantially intact.
Subsequently, a layer of the electrically conductive material may be formed over the semiconductor structure 100 by means of a known deposition process, and a further chemical mechanical polishing process may be performed to remove portions of the layer of the electrically conductive material outside the contact vias 115-120.
A problem of the method of forming a semiconductor structure according to the state of the art described above is that the stress created by the intrinsically stressed etch stop layer 113 may be relatively weak, or may be insufficiently transmitted to portions of the substrate 101 below the gate electrodes 106, 206.
A further problem of the method of forming a semiconductor structure according to the state of the art described above is that both the first transistor element 102 and the second transistor element 202 are exposed to the stress created by the stressed etch stop layer 113. If the first transistor element 102 and the second transistor element 202 are transistors of a different type, the stress created by the stressed etch stop layer 113 may be adapted to improve the charge carrier mobility in one of the transistor elements 102, 202. For example, in case the first transistor element 102 is a P-type transistor and the second transistor element 202 is an N-type transistor, a compressive stress of the etch stop layer 113 may help to improve the performance of the first transistor element 102, but may have no influence on the performance of the second transistor element 202 or may even be detrimental to the performance of the second transistor element 202. Conversely, an intrinsic tensile stress of the etch stop layer 113 may help to improve the performance of the second transistor element 202 when being an N-type transistor, but may have no influence on the performance of the first transistor element 102 when being a P-type transistor or may even be detrimental to the performance of the first transistor element 102.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.